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Layered Self-Timed Interfaces for IC Systems

Doctor of Philosophy in Electrical Engineering (Applied Physics)
University of California, San Diego, 1993
Professor Walter H. Ku, Chair

The continuous trend toward massive device integration has shifted the costs (area and energy) of integrated circuit systems from the active devices to interconnect wires.  As a result, it has become attractive to compose systems such that each module's speed performance is limited by its own internal structure rather than the overall system size.  This design paradigm has historically caused a bottleneck in I/O bandwidth.  In this research, we focus on inter-module communications independent of each module's complexity.

This dissertation introduces a formal technique by which layered self-timed interfaces for CMOS integrated circuits can be designed and optimized.   A framework which defines the concept of layered self-timed interfaces is given along with a guiding taxonomy for the design optimization of such interfaces.  This framework and the guiding design optimization taxonomy are utilized to introduce a new wide-bus self-timed simultaneous bi-directional interface for integrated circuit systems.  As an application to array processing we introduce a new Two-Wave Wavefront Array Processor which reduces the computational latency by a factor of two and doubles the throughput rate over conventional Wavefront Array Processors. 

The design optimization of layered self-timed interfaces utilizes analytical techniques based on solutions to the Telegraph equation where each communication channel, i, within a layered interface is characterized by a 3-vector attribute.  The design approach consists of formulating a standard constrained nonlinear optimization problem and solving it numerically to define the size of the layered interface.  We consider a hybrid objective function which encompasses RC and transmission-line delay domains.  This permits rapid convergence to an approximate solution for the values of driver, interconnect, and receiver impedances, before the circuit-level design and analysis phase begins.