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A compact array processor based on self-timed simultaneous bidirectional signalling
- Yacoub, G.Y.; Soni, T.; Ku, W.H.
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
This paper appears in: Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
On page(s): 1893 - 1896 vol.3
3-6 May 1993
May 1993
ISBN: 0-7803-1281-3
Number of Pages: 4 Vols., 2829
References Cited: 10
INSPEC Accession Number: 4996988
A bundled self-timed simultaneous bidirectional signaling protocol is used to remove the clock dependency and minimize latency in the communication network of an array processor. The use of the same data for bidirectional data transfer effectively doubles the I/O bandwidth of such a communication network. This also permits making the input data transfer cycles independent of the output data transfer cycles, thus decoupling the data and resulting waves in a wavefront array processor. As a vehicle to demonstrate the merit of this protocol and to compare it to the more conventional wavefront array based processing (WAP) protocols, the design of a two-dimensional array processing structure for matrix multiplication using such a protocol is described. A computation element based on a bit-serial multiplier accumulator is chosen with a data dependent computation time. This permits the design of an array where neither the computation nor the communication speeds are bound by any clock speeds. It is shown that such an approach reduces the latency of the array structure without increasing I/O pin count.
Index Terms:
parallel processing; VLSI; multiprocessor interconnection networks; protocols; matrix multiplication; computational complexity; compact array processor; self-timed simultaneous bidirectional signalling; signaling protocol; clock dependency; latency; I/O bandwidth; input data transfer cycles; two-dimensional array processing; matrix multiplication; bit-serial multiplier accumulator; data dependent computation time


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