Self-timed simultaneous bidirectional signalling
for IC systems
- Yacoub, G.Y.; Ku, W.H.
California Univ., San Diego, CA, USA
This paper
appears in: Circuits and Systems, 1992. ISCAS '92.
Proceedings., 1992 IEEE International Symposium on
On
page(s): 2957 - 2960 vol.6
3-6 May
1992
1992
Volume: 6
ISBN:
0-7803-0593-0
Number of Pages: 6 vol. 3028
References Cited: 9
INSPEC Accession Number:
4417402
Abstract:
The authors present a self-timed architectural
interface design for VLSI CMOS integrated circuit systems. The
interface follows a two-cycle self-timed bundled data protocol and
nearly doubles the input/output (I/O) bandwidth for wide bus VLSI
interprocessor communication by simultaneously sending and receiving
data over the same wires. A constant overhead of four control wires
is incurred over the synchronous approach proposed by K. Lam et al.
(1990), as well as a decaying area penalty for increasing bus
widths. This type of self-timed bundled interface can prove
attractive for applications where global synchronization is
difficult to achieve. The interface has been simulated for a 16-b
wide bus using a quasi-analog mixed-signal Verilog approach.
Index Terms:
simultaneous bidirectional signalling; IC
systems; self-timed architectural interface design; VLSI CMOS;
integrated circuit systems; two-cycle self-timed bundled data
protocol; wide bus; VLSI interprocessor communication;
synchronization; CMOS integrated circuits; digital integrated
circuits; synchronisation; VLSI |
